As CMOS devices continue downscaling, effects of short channel effect and carrier mobility degradation effect of the devices become increasingly prominent. Demands on capabilities for suppressing the short channel effect and increasing the carrier mobility of the devices as required by development of the silicon-based MOS technology are getting pressing.
At present, in order to suppress the short channel effect of a device, conventional methods mainly include increasing a doping concentration of a substrate, adding a source/drain light doped region (LDD region), introducing a pocket structure, and the like; and meanwhile, an ultra-thin body structure can also be used in a silicon-on-insulator (SOI) device. However, increasing the doping concentration of the substrate will increase a threshold voltage of the device and decrease an on-state current of the device, adding the LDD region will increase a parasitic resistance of the device, and likewise, adding the pocket structure will cause an increase of a doping level of the substrate; and employing the ultra-thin body structure will cause an increase of the source/drain series resistance, and at the same time, will cause a great decrease of the channel carrier mobility and an overdriving capability of the device due to an increase of an interface scattering and a self-heating effect, and so on.
Meanwhile, when the dimensions of the device downscale to sub-100 nm regime, a deterioration of the short channel effect of the device makes it very difficult to implement a method for obtaining a better performance by further scaling. In order to relieve the problem caused by downscaling of the device, a strained silicon technology has been used to introduce a stress into the channel, and thus the carrier mobility of the channel and the device performance of a transistor are improved. Such a method has become indispensable and has been widely adopted in the field of microelectronics fabrication industry. The basic principle of the method is described as follows: a stress is introduced in a channel region of a transistor by means of a structure, a material and a process design of the device, so that a lattice structure of the channel portion of the substrate is changed, thereby a mobility of carriers in the channel is increased.
The strain technology lies on that how to introduce a stress as needed by the device into the channel. A typical structure of a field effect transistor is shown in FIG. 1. Generally, with respect to such a device structure, conventional methods for introducing the stress mainly comprise following methods: 1) A strain is introduced by using a Si/SiGe heterojunction substrate; that is, as shown in FIG. 2(a), by using a non-silicon (non-Si) substrate, such as a SiGe substrate, a stress is introduced into a channel layer by using a difference between lattices of the substrate and the surface Si channel layer. At this time, lattices of the surface Si channel layer are stretched by lattices of SiGe of a lower layer because a lattice constant of SiGe is larger than that of Si, thus the stress is introduced into the Si channel. 2) A stress is introduced into the channel portion by using a heterojunction source/drain structure; that is, as shown in FIG. 2(b), by substituting the Si material in the source/drain regions with a non-silicon (non-Si) material, SiGe, for example, the stress is induced in the channel by heterojunctions between the source/drain and the channel. 3) A stress is introduced into the channel in the substrate by covering a highly strained layer on the device; that is, as shown in FIG. 2(c), a layer of highly strained film is applied on the device, and a strain of the film itself induces a strain in the device beneath the thin film, so that the stress is introduced into the channel.
It should be noted that, the foregoing methods do not substantially improve the device structure, and cannot effectively improve the capability for suppressing the short channel effect of the device itself.